Flash memory devices have found growing commercial success in the electronic device market due in part to the ability of flash memory devices to store electronic data over long periods of time without an electric power supply. Additionally, flash memory devices can be erased and programmed over multiple write cycles by an end user after they have been installed in an electronic device. This combined functionality is especially useful in electronic device applications such as cellular telephones, personal digital assistants, computer BIOS storage, etc., where power supply is intermittent and programmability and data retention are desired.
Flash memory technology evolved from electrically erasable read only memory (EEPROM) chip technology, which can be erased in situ. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased in fixed multi-bit blocks or sectors.
One type of flash memory device is constructed in a cell structure wherein a single bit of information is stored in each cell. FIG. 1 is a cross section view of an exemplary flash memory device. Memory device 100 is comprised of a substrate 101 having a source region 102 and a drain region 103. Typically, substrate 101 is a crystalline silicon semiconductor substrate which has undergone an N-type (electron rich) doping in source region 102 and drain region 103. Memory device 100 further comprises a gate array 104. In the embodiment of FIG. 1, gate array 104 is comprised of a tunnel oxide layer 105, a floating gate 106, and insulating layer 107, and a control gate 108. A channel region 109 underlies gate array 104 between source region 102 and drain region 103.
The single bit stacked gate flash memory cell (e.g., memory cell 100 of FIG. 1) is typically programmed by “channel hot electron injection” in which a high positive voltage is applied to control gate 108, source 102 is coupled to ground and drain 103 is coupled to a positive voltage. The resulting high electric field across the channel region accelerates electrons toward the drain region and imparts enough energy for them to become hot electrons. The hot electrons are scattered (e.g., by impurities or the substrate lattice structure of the substrate in the channel region) and are redirected toward the floating gate by the vertical field established by the positive control gate voltage. If the electrons have enough energy, they can tunnel through gate oxide 105 into floating gate 106 and become trapped there. This changes the threshold voltage VT, and thereby the channel conductance, of memory cell 100.
Memory cell 100 is read by connecting the source region 102 to ground, raising the voltage at the control gate 108 to the sense level and connecting the drain region 103 to a sense amplifier; if memory cell 100 is programmed, no current flows to the sense amplifier.
In order to erase memory cell 100, a voltage (e.g., 10 to 12 volts) is applied to source region 102, control gate 108 is held at a negative potential, and drain region 103 is allowed to float. Under these conditions, an electrical field is developed across tunnel oxide 105 between floating gate 106 and source 102. The electrons that are trapped in floating gate 106 flow toward and cluster at the portion of floating gate 106 overlying source region 102. The electrons are then extracted from floating gate 106 and into source region 101 by way of Fowler-Nordheim tunneling through tunnel oxide 105. Memory cell 100 is erased as the electrons are removed from floating gate 106.
More recently, dual bit flash memory devices have been introduced that allow the storage of two bits of information in two separate cells of a single memory device. The dual bit flash memory device uses what is known as a virtual ground architecture in which the source of one cell in the device serves as the drain of the other cell. FIG. 2 illustrates an exemplary prior art dual bit memory cell 200. Memory cell 200 comprises a silicon nitride layer 201 which is disposed between a top silicon dioxide layer 202 and a bottom silicon dioxide layer 203, forming an ONO layer 204. A polysilicon layer 205 resides over the ONO layer 204 and provides a wordline connection to the memory cell 200. The structure comprising ONO layer 204 and polysilicon layer 205 is also referred to as a nitride gate array. A first bitline 206 and a second bitline 207 run underneath the ONO layer 204. Memory cell 200 resides on P-type substrate 208 with the conductive portion of the bitlines 206 and 207 formed from an N+ implant, such that a channel 209 is formed across the P-type substrate 208 when the bitlines are biased. Memory cell 200 is a single transistor having interchangeable source and drain components formed from bitlines 206 and 207 with a gate formed as part of a polysilicon wordline 205.
Silicon nitride layer 201 forms a charge trapping layer. The programming of dual bit memory cell 200 is done by channel hot electron injection, which stores a localized charge in the oxide-nitride interface of ONO layer close to the drain side of the cell. Since the silicon nitride layer 201 is non-conducting, a first charge can be injected into silicon nitride layer 201 near the junction of bitline 206 and ONO layer 204 and stored as left bit 210. Similarly, and a second charge can be injected and stored in silicon nitride layer 201 near the junction of bitline 207 and ONO layer 204 and stored as right bit 211.
The dual bit memory cell 200 is symmetrical allowing the drain and the source to be interchangeable. Thus, bitline 206 may serve as the drain terminal and bitline 207 may serve as the source terminal when programming left bit 210. Likewise, bitline 207 may serve as the drain terminal and bitline 206 may serve as the source terminal for programming right bit 211.
FIG. 3 shows an exemplary flash memory array. Typically, a flash memory array is comprised of rows of memory cells (e.g., memory cell 100 of FIG. 1) in which the control gates (e.g., control gate 108 of FIG. 1) of the memory cells are coupled by a common wordline (e.g., wordlines 310 of FIG. 3). Similarly, the drain regions (e.g., drain region 103 of FIG. 1) are coupled in columns by a common bitline (e.g., bitlines 320 of FIG. 3). Each column of the memory cells is isolated from adjoining columns by an insulating layers such as a shallow trench isolation structures 390 in the substrate that run between and parallel to bitlines 320.
A plurality of source lines 350 extend in the row direction, that is parallel to wordlines 310 and couple the source regions 102 of adjoining memory cells in a row. One source region may be shared as a common source region in adjoining rows of memory cells. Similarly, one drain region may be shared as a common drain region in adjoining rows of memory cells. A plurality of source contacts 360 (also referred to as Vss pickups or Vss contacts) supply electrical current to the source regions of the memory cells.
Usually, in order to reduce the resistance, dopants are implanted in the Vss diffusion at a greater concentration. However, this leads to a deeper source region doping profile which shortens the channel region (e.g., channel region 109 of FIG. 1). As the channel length between the source region 102 and drain region 103 is decreased, the memory cells may exhibit undesirable characteristics that are commonly referred to as “short channel effects.” For example, controlling unintended electrostatic interactions between the source and drain is more difficult to control in short-channel devices because the threshold voltage (VT) of the device is lowered in short channel devices. Additionally, as the drain bias is increased, the drain depletion region widens into the channel and can merge with the source depletion region. This results in punch-through leakage between the source and drain and loss of gate control over the memory cell. This encroachment of the depletion region from the drain into the channel is known as Drain Induced Barrier Lowering (DIBL) and is becoming increasingly problematic as the size of memory cells continues to shrink.
An increase in leakage current is especially problematic in flash memory devices as they are widely used in very low power applications, for example mobile telephones, due to the ability of flash memory to retain information without applied power. Increases in leakage current may significantly increase total power consumption of a product using the flash device.
FIG. 4 is a cross section view of an exemplary prior art flash memory device 400. A conventional flash memory device comprises an array of memory cells (e.g., memory cells 421, 422, and 423 of FIG. 4) that is commonly referred to as the “core array” (e.g., core array 420 of FIG. 4). Additional components are commonly referred to as the “periphery devices” (e.g., devices 411 and 412 of FIG. 4) are disposed outside of the core array (e.g., in periphery region 410 of FIG. 4) and are typically used for a variety of tasks such as logic functions, state machines, data management, selector switches, addressing decoders (e.g., x-line address decoders and y-line address decoders), high voltage generators, etc. In order to reduce the size and power consumption of flash memory devices, manufacturers have concentrated upon decreasing the size of the memory cells. For example, smaller gate arrays and shorter channel lengths (e.g., channel length 453 of FIG. 4) facilitate more compact memory arrays that require less power. However, while the size of the memory cells has been decreasing, the size of the periphery devices has essentially remained unchanged. This is due, in part to the fact that shrinking the size of the periphery devices does not result in a corresponding shrinking of the overall size of the flash memory device because of the relatively fewer components involved. Thus, periphery devices are characterized by larger gate arrays and longer channel lengths (e.g., channel length 443 of FIG. 4) relative to the scale of the memory cells.
In a conventional fabrication process, the implanting of dopants is performed in the core region before the implanting of dopants in the periphery is performed. Because of the different scales of the devices, different process parameters are necessitated for implanting of the dopants. Following the implanting of the periphery dopants, an annealing process is performed which activates the dopants and diffuses them into the substrate. The process parameters of the annealing determine some of the electrical characteristics of the semiconductor structures such as junction depth, resistance, and activation of the dopants. For example, the depth to which dopants are diffused in the source and drain of a periphery device (e.g., source 441 and drain 442 of FIG. 4) may require a different set of time and temperature parameters than the annealing process needed to diffuse the dopants in the source and drain areas of the memory cells (e.g., source 451 and drain 452 of FIG. 4). Ideally, all of the semiconductor devices would be sized nearly identically (e.g., similar channel lengths, similar doping profiles, similar junction depths, similar resistance, etc.). However, as stated above, the memory cells in the core are scaled differently than the devices in the periphery region. As a result, an annealing process that is optimized for the core cells may not be adequate for the periphery devices. For example, a shorter annealing process may be appropriate for the core cells to avoid short channel effects that result from excessive diffusing of the dopants in the core array. However, the relatively larger structures in the periphery require different optimal process parameters such as the length and/or temperature of the annealing process. Similarly, an annealing process optimized for the periphery devices may exceed optimal parameters for the core cells. For example, an overly long annealing process may cause excessive diffusion of the dopants in the source and drain regions and result in short channel effects being exhibited in the memory cells.
Thus, conventional methods for fabricating flash memory devices are disadvantageous in that the annealing process results in dopant diffusion profiles that are not optimal for the core cells and/or the periphery cells.